The main way of describing how densely transistors are packed is in terms of "feature size", which is roughly the size of the smallest geometric feature that can be produced. In the current state of the art, with the latest Intel Pentium processor chips, for example, the smallest feature size is 65 nanometers (nm).
In the process of semiconductor fabrication features are created through the process of photolithography. In essence, this amounts to printing the circuits containing all transistors and their interconnections on a semiconductor material in much the same way as photographic images have long been printed on paper.
The main problem with printing very small features using light is the phenomenon of diffraction, which makes it very difficult to print features that are substantially smaller than the wavelength of light. The shortest wavelength of visible light is about 400 nm (violet), which is totally inadequate for feature sizes such as 65 nm.
The current state of the art uses ultraviolet light with wavelengthts of 248 or 193 nm ("deep ultraviolet"). This is just barely able to handle feature sizes of 65 nm by using various tricks of "nanolithography", such as "liquid immersion". It is expected that by 2009 this process will be capable of creating feature sizes of 45 nm. Intel has already demonstrated an experimental system that can do this.
But that's not going to be good enough beyond 2009. New techniques of producing smaller feature sizes around 10 to 30 nm (just a few hundred atoms in width) are now the subjects of active research. Intel is investigating techniques of extreme ultraviolet lithography which, the company hopes, will achieve feature size objectives, using ultraviolet light with a wavelength of only 13.5 nm, by 2009. (See here.)
That approach, however, is not the only one possible. Other laboratories are claiming features sizes of 26 nm already, using other techniques:
Breakthrough Computer Chip Lithography Method Developed at RIT
Leading a team of engineering students, Bruce Smith, RIT professor of microelectronic engineering and director of the Center for Nanolithography Research in the Kate Gleason College of Engineering, developed a method—known as evanescent wave lithography, or EWL—capable of optically imaging the smallest-ever semiconductor device geometry. Yongfa Fan, a doctoral student in RIT’s microsystems engineering Ph.D. program, accomplished imaging rendered to 26 nanometers —a size previously possible only via extreme ultraviolet wavelength, Smith says. By capturing images that are beyond the limits of classical physics, the breakthrough has allowed resolution to smaller than one-twentieth the wavelength of visible light, he adds.
Tags: semiconductor fabrication, photolithography, nanolithography, extreme ultraviolet lithography, evanescent wave lithography
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